1. Field of the Invention
The present invention relates to an array of three-terminal switches formed in a thin semiconductor film, such as an array of light-emitting thyristors formed in a thin compound semiconductor film; to a combined semiconductor device combining this type of thin-film array and its driving circuitry; and to an image-forming device having combined semiconductor devices of the invented type.
2. Description of the Related Art
Arrays of light-emitting elements are used as light sources in electrophotographic printers. In a conventional electrophotographic printer of this type, the light-emitting elements are light-emitting diodes (LEDs) that form an electrostatic latent image by selectively illuminating a charged photosensitive drum responsive to print data. The image is then developed by applying toner to the photosensitive drum, the toner image is transferred from the photosensitive drum onto paper, and the image is fused onto the paper by heat and pressure.
The control circuitry of an electrophotographic printer of the LED type is shown in FIG. 1. The print control unit 101, which comprises a microprocessor, read-only memory (ROM), random-access memory (RAM), input-output ports, timers, and so on disposed in the printing engine of the printer, receives a control signal SG1, a one-dimensionally mapped dot data signal referred to as a video signal SG1, and other signals from a host controller (not shown), and executes printing operations by carrying out overall sequence control of the printer. More specifically, the print control unit 101 controls a pair of drivers 102, 104 that drive respective stepper motors or pulse motors (PM) 103, 105 according to signals received from sensors 106-109, sends print data and commands to an LED head 119, controls the temperature of a fuser 122 with an internal heater 122a according to signals from a temperature sensor 123, and controls a pair of high-voltage (HV) power supplies 125, 126 that supply high negative and positive potentials, respectively, to a developer 127 and transfer unit 128.
The printing process is carried out as follows. Upon receiving a printing command in the control signal SG1, the print control unit 101 reads the fuser temperature sensor 123, and if necessary, turns on the heater 122a to raise the fuser 122 to the temperature necessary for fusing. Next, the print control unit 101 activates driver 102 to drive the development and transfer process motor 103, issues a charge signal SGC that turns on power supply 125 to charge the developer 127, and checks the paper sensor 108. If paper is present, driver 104 is activated to drive the paper transport motor 105, first in reverse to pick up a sheet of paper, then forward to bring the paper past the paper pick-up sensor 106 and into the printing mechanism of the printer. Driver 104 is controlled according to the paper size, which is sensed by the paper size sensor 109.
When the paper reaches a printable position, the print control unit 101 sends a timing signal SG3 (including a main scanning synchronization signal and a sub-scanning synchronization signal) to its host controller and begins receiving a video signal SG2 including the print data for one page. The print data are transferred to the LED head 119 a line at a time. When one line of print data has been loaded into the LED head 119, it prints the line by selectively illuminating the photosensitive drum (not shown) while receiving the print data for the next line. The photosensitive drum is negatively charged, but charge escapes from the illuminated dots. The illuminated dots are accordingly at a higher potential than the non-illuminated parts of the photosensitive drum and attract toner, which is negatively charged in the developer 127, to form a toner image.
Rotation of the photosensitive drum brings the toner image to the transfer unit 128; in the meantime, a transfer signal SG4 turns on power supply 126, which supplies a strong positive potential to the transfer unit 128. The toner image is transferred onto the paper as the paper is transported between the photosensitive drum and the transfer unit 128.
The paper carrying the transferred toner image is next transported to and pressed against the fuser 122, which has been heated by its internal heater 122a. The heat fuses the toner image onto the paper. The paper carrying the fused image passes the delivery sensor 107 and is ejected from the printing mechanism of the printer.
The print control unit 101 uses the information from the paper size sensor 109 and the paper pick-up sensor 106 to time the operation of the transfer power supply 126 so that the transfer unit 128 receives power only while paper is passing through it. When printing is completed and when the paper has passed the delivery sensor 107, the charging voltage power supply 125 stops powering the developer 127, and the development and transfer process motor 103 stops turning.
This operation is repeated for each printed page.
Next the technical background and operation of the LED head 119 will be described. An LED is one of several known types of light-emitting elements. Other examples include laser diodes and negative-resistance elements such as light-emitting thyristors and laser thyristors.
An LED has a pn or p-i-n junction formed by doping of a compound semiconductor material such as gallium arsenide (GaAs), gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium aluminum arsenide (InGaAlAs), etc. Carriers are injected into the junction by applying a forward voltage, and light is emitted by a carrier recombination process.
A laser diode (LD) is structured like an LED with an internal waveguide. When current exceeding a threshold level is fed through it, enough electron-hole pairs are formed to create a population inversion in which photon multiplication (light amplification) by stimulated radiation occurs, a phenomenon known as lasing. The light gains in intensity as it travels back and forth between parallel mirrors formed on, for example, the cleaved ends of the diode, repeatedly reentering the active region, and a laser beam is output from the ends of the waveguide.
A light-emitting thyristor having a pnpn structure formed by a compound semiconductor is described by Shoji Aoki in Hakko Daiodo (Light-Emitting Diodes), Kogyo Chosakai Publishing Co., Ltd., pp. 167-169.
As an example of the prior art, an LED head disclosed in Japanese Patent Application Publication No. 2000-108407 for printing on paper of A4 size with a resolution of 600 dots per inch will be explained with reference to FIG. 2.
The part CHP1 enclosed by the dotted line in FIG. 2 is an LED array chip including one hundred ninety-two LEDs (LED1 to LED192). The part DRV1 enclosed by the dash-dotted line is a driving IC for driving the LEDs and has drive electrodes DO1 to DO192.
The LED head 119 in FIG. 1 is an array of twenty-six identical LED array chips (CHP1 to CHP26, not shown in FIG. 1) containing one hundred ninety-two LEDs each, and twenty-six identical driving ICs (DRV1 to DRV26, not shown in FIG. 1) which are connected in cascade. FIG. 2 shows the first stage, comprising driving IC DRV1 and LED array CHP1. The other driving ICs (DRV2 to DRV26, not shown) and LED arrays (CHP2 to CHP26, not shown) are configured in the same way.
The first driving IC (DRV1) receives a load control signal (LOAD), a clock signal (CLK), four data signals (DATAI0, DATAI1, DATAI2, DATAI3), and a strobe signal (STB) from the print control unit 101 in FIG. 1 and a reference voltage VREF from a regulator circuit (not shown) in the LED head, and generates four data output signals (DATAO0, DATAO1, DATAO2, DATAO3) which are supplied to the data input terminals (DATAI0, DATAI1, DATAI2, DATAI3) of the second driver IC (DRV2, not shown). The data output terminals DATAO0-DATAO3 of driving IC DRV2 are similarly connected to the data input terminals DATAI0-DATAI3 of the third driving IC DRV3 (not shown) and so on. These interconnections are made by wire bonding and printed wiring on a printed circuit board on which the driver ICs and LED arrays are mounted. The load, strobe, and clock signals are supplied to all of the driver ICs from the print control unit 101.
The dash-dotted line in FIG. 2 encloses an internal block diagram that applies to each driving IC (DRV1 to DRV26). Flip-flop circuits FFA1 to FFA49, FFB1 to FFB49, FFC1 to FFC49, and FFD1 to FFD49 form shift-register circuits operated by the clock signal input from the CLK terminal. Latch circuits LTA1 to LTA48, LTB1 to LTB48, LTC1 to LTC48, LTD1 to LTD48 are operated by a latch signal LOAD-P (the ‘P’ indicates positive logic) input from the LOAD terminal.
The reference characters SEL denote a selector circuit, reference characters 131 and 132 denote inverter circuits, 133 denotes an AND gate, and 134 denotes a resistor. Reference characters MEM1 to MEM193 denote memory circuits, DR1 to DR192 denote driving circuits of the LED elements, ADJ denotes a control voltage generating circuit, and CTRL denotes a write control circuit for memories MEM1 to MEM193.
Memories MEM1 to MEM192 store dot correction data for adjusting the driving current supplied to the LEDs through LED drive terminals DO1 to DO192. The driving current is adjustable in sixteen levels. Memory MEM193 stores chip correction data for adjusting the LED driving current value of the entire driving IC in sixteen levels. These memories are provided for the following reason.
The light emitting efficiency of the LED arrays used in an LED head (and thus the amount of light emitted) generally show considerable variation both from chip to chip and from dot to dot. Because these variations in the amount of light degrade the printing quality of the printer, the driving current output by the driving ICs must be adjustable both by chip and by dot (LED) so that the variations can be corrected. Memories MEM1 to MEM192 and MEM193 store dot correction data and chip correction data used for that purpose.
Latch circuits LTA1 to LTA48 latch the data signals stored in flip-flop circuits FFA1 to FFA48. Latch circuits LTB1 to LTB48, LTC1 to LTC48, and LTD1 to LTD48 latch the data signals stored in flip-flop circuits FFB1 to FFB48, FFC1 to FFC48, and FFD1 to FFD48, respectively.
Flip-flop circuits FFA1 to FFA49 are connected in cascade. The data input terminal (D) of FFA1 is connected to data input terminal DATAI0 of the driving IC, and the data output terminal (Q) of FFA48 is connected through the selector (SEL) to data output terminal DATAO0 of the driving IC. Flip-flop circuits FFB1 to FFB48, FFC1 to FFC48, and FFD1 to FFD48 are also separately connected in cascade. The data input terminals (D) of flip-flop circuits FFB1, FFC1, and FFD1 are connected to data input terminals DATAI1, DATAI2, and DATAI3, respectively, of the driving IC, and the outputs from FFB48, FFC48, and FFD48 are respectively connected through the selector circuit (SEL) to data output terminals DATAO1, DATAO2, and DATAO3 of the driving IC.
Accordingly, flip-flop circuits FFA1 to FFA49, FFB1 to FFB49, FFC1 to FFC49, and FFD1 to FFD49 form respective forty-nine-stage shift registers. The number of shift stages of the shift register can be switched between forty-eight and forty-nine in accordance with the signal level at the LOAD terminal.
In the driving IC shown in FIG. 2, data terminals DATAI3 to DATAI0 and DATAO3 and DATAO0 are used to transfer both print data and correction data. When the correction data are transferred, the LOAD terminal is brought high to set the shift register to forty-nine-stage operation (one stage greater than in print data transfer) so that chip correction data can be transferred in addition to the dot correction data.
The outputs of the LED driving circuits DR1 to DR192 are connected to driving current output terminals DO1 to DO192 of the driving IC. Corresponding LED elements LED1 to LED192 are connected by wire bonding or by a sputtered metallization layer.
Japanese Patent Application Publication No. 2004-207444 (hereinafter, JP/2004-207444) describes another type of LED head that can be used as the LED head 119 in FIG. 1. Referring to FIG. 3, this LED head has combined semiconductor chips 200, each combining a thin-film LED array 206 and its driving circuitry. The combined semiconductor chips 200 are mounted on a glass epoxy printed circuit board 220 to which they are electrically coupled by bonding wires 221. The mounting may be effected by, for example, an insulating or a conductive adhesive paste. The thin-film LEDs 206 are fabricated as epitaxial films (epi-films) on a separate compound semiconductor substrate, then detached from that substrate and attached to the silicon substrates of the combined chips 200. The LEDs in the epi-films 206 are equally spaced in a single row, and the combined semiconductor devices 200 are mounted on the printed circuit board 220 in such a manner that the LEDs form a single equally spaced linear array extending for substantially the entire length of the LED unit 240.
Disposed also on the printed circuit board 220 are printed wiring (not shown) and bonding pads (not shown) for supplying power, data, and control signals to the combined semiconductor chips 200. The silicon substrate of each combined chip 200 has bonding pads for receiving the power, data, and control signals. The bonding wires 221 connect the bonding pads on the printed circuit board 220 to the bonding pads on the combined chips 200.
FIG. 4 is a plan view showing part of one of the combined semiconductor chips 200. FIG. 5 is a sectional view through line A1-A1′ line in FIG. 4. FIG. 6 is a sectional view through line A2-A2′ line in FIG. 4.
As shown in FIGS. 4 to 6, the combined chip 200 has a monolithic silicon substrate 201 in which an integrated circuit 202 is formed, a first interlayer dielectric film 203 formed on the silicon substrate 201, an adhesive layer 204 formed mainly from a semiconductor material on the interlayer dielectric film 203, and a ground plane 205 formed on the adhesive layer 204. The thickness of the silicon substrate 201 is, for example, about 300 μm.
The combined chip 200 includes a plurality of LED epitaxial films or epi-films 206, which were shown schematically as a single film in FIG. 3. The LED epi-films 206 are bonded onto the ground plane 205. A discrete electrode 207 extends from each LED epi-film 206 to a discrete terminal area 208 of the integrated circuit 202 to electrically connect the LED epi-film 206 and the integrated circuit 202. A second interlayer dielectric film 209 (FIG. 6) for electrically insulating the discrete electrodes 207 from part of the silicon substrate 201 and the LED epi-films 206 is disposed where insulation is needed, such as between the discrete electrode layer and the ground plane 205 and between the discrete electrode layer and the adhesive layer 204.
Each of the LED epi-films 206 has an appropriate semiconductor multilayer structure such as a hetero-epitaxial layer structure so that it functions as an LED. As shown in FIG. 4, the LED epi-films 206 are arranged at equal intervals the linear array.
The LED epi-film 206 has a thickness of about 2 μm, which is adequate for providing stable light-emitting and electrical properties.
The integrated circuit 202 formed in the silicon substrate 201 has substantially the same circuit configuration as DRV1 in FIG. 2. The driving circuits (DR1 . . . ) are disposed facing the LED epi-films 206 that they drive.
The integrated circuit 202 is formed in the upper part of the silicon substrate 201, within the dotted line in FIG. 5. As in FIG. 2, the integrated circuit 202 contains numerous memory elements and other types of circuit elements. To accommodate these circuit elements, the width W of the silicon substrate 201 greatly exceeds the width W1 of the epi-film.
The first interlayer dielectric film 203 shown in FIG. 5 can be a single-layer or multilayer structure containing at least either a silicon-oxide (SiO2) layer or a silicon-nitride (Si3N4) layer. The first interlayer dielectric film 203 electrically insulates the surface of the silicon substrate 201 from the LED epi-films 206, so that the LED epi-films 206 can function normally. The interlayer dielectric film 203 and the integrated circuit 202 occupy separate but adjacent surface areas of the silicon substrate 201.
The adhesive layer 204 is a semiconductor layer such as a polycrystalline silicon layer or an amorphous silicon layer formed by chemical vapor deposition (CVD). The adhesive layer 204 has high affinity for the interlayer dielectric film 203, and provides a high adhesion strength between the adhesive layer 204 and the first interlayer dielectric film 203.
The ground plane 205 may be a metal layer of a material such as gold or palladium. The adhesive layer 204 also has high affinity for the ground plane 205, providing high adhesion strength between the adhesive layer 204 and the ground plane 205. The LED epi-films 206 are affixed to the surface of the ground plane 205.
The ground plane 205 both holds the LED epi-films 206 firmly attached and connects them electrically to a common terminal (such as a ground pad) located on the silicon substrate 201. An ohmic contact is preferably formed between the ground plane 205 and the lower surfaces of LED epi-films 206. The ground plane 205 can be electrically connected to the common (e.g. ground) terminal area by wiring 332 as in FIG. 11, or through an opening (not shown) in the first interlayer dielectric film 203.
The ground plane 205 is electrically connected to each LED epi-film 206 through the entire under-surface of the LED epi-film 206, more specifically, through the entire surface of the n-type GaAs layer 211 shown in FIG. 6, which functions as a cathode electrode (n-electrode). The common terminal area on the silicon substrate 201 is a common return terminal for the driving current supplied to drive the LEDs.
As shown in FIG. 6, the combined chip 200 has a multi-layer structure including the silicon substrate 201, the first interlayer dielectric film 203, the adhesive layer 204, the ground plane 205, the LED epi-films 206, the second interlayer dielectric film 209, and the discrete electrode layer 207, in that order. Each LED epi-film 206 has a multilayer structure including an n-type GaAs contact layer 211, an n-type AlxGa1-xAs lower cladding layer 212 (0≦x≦1), an n-type AlyGa1-yAs active layer 213 (0≦y≦1), an n-type AlzGa1-zAs upper cladding layer 214 (0≦z≦1), and a p-type GaAs contact layer 215 formed in that order. A p-type zinc diffusion region 216 is formed in the n-type AlyGa1-yAs layer 213 and the n-type AlzGa1-zAs layer 214 beneath the p-type GaAs layer 215.
The n-type GaAs layer 211 has a thickness of about 10 nm (=0.01 μm). The n-type AlxGa1-xAs layer 212 has a thickness of about 0.5 μm. The n-type AlyGa1-yAs layer 213 has a thickness of about 1 μm. The n-type AlzGa1-zAs layer 214 has a thickness of about 0.5 μm. The GaAs layer 215 has a thickness of about 10 nm (=0.01 μm). The LED epi-film 206 accordingly has, in this case, a thickness of about 2 μm.
A process for fabricating the LED epi-film 206 will next be described with reference to the sectional views in FIGS. 7 and 8.
In FIG. 7, an LED epitaxial layer 206a, which will be partially removed to form LED epi-films 206, is grown by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). First a GaAs buffer layer 222, an (AlGa)InP etching stop layer 223, and an AlAs separation layer 224 are deposited in succession on a GaAs substrate 221. The GaAs substrate 221, GaAs buffer layer 222, and (AlGa)InP etching stop layer 223 form an LED epi-film fabrication substrate 324. Then the lower contact layer (n-type GaAs layer) 211, lower cladding layer (n-type AlxGa1-xAs layer) 212, active layer (n-type AlyGa1-yAs layer) 213, upper cladding layer (n-type AlzGa1-zAs layer) 214, and upper contact layer 215 (at this stage an n-type GaAs layer 215) are deposited on the AlAs separation layer 224 in this order.
The LED epitaxial layer 206a is now removed by chemical lift-off. First, the GaAs layers 211 to 215 are etched to form trenches, one of which is shown in FIG. 8. The trenches 225 are formed by photolithography using, for example, a resist mask patterned to define the trench areas and an etching solution of phosphoric acid and hydrogen peroxide. The solution of phosphoric acid and hydrogen peroxide readily etches the GaAs and AlGaAs layers 211 to 215, but the etching rate of (AlGa)InP is slow, so that trench formation stops at the (AlGa)InP etching stop layer 223 and does not proceed into the GaAs buffer layer 222 of the fabrication substrate 324.
After the trenches 225 are formed, the AlAs separation layer 224 is etched with a 10% hydrofluoric acid (HF) solution. Because the HF etching rate of the AlAs separation layer 224 is much higher than the HF etching rate of the GaAs, AlGaAs, and (AlGa)InP layers 211 to 215 and 221 to 223, the AlAs separation layer 224 can be etched selectively, leaving the LED epi-films 206 substantially intact but detaching them from the LED epi-film fabrication substrate 324. FIG. 8 shows an intermediate stage in which the LED epi-films are still partly attached to the fabrication substrate 324 by the AlAs separation layer 224. When the etching process is completed, the AlAs separation layer 224 is completely removed and the LED epi-films 206 are held from above in, for example, the manner described below.
Before the LED epi-films 206 are removed, supporting members may be formed on their surfaces for support and protection. If such supporting members are formed on the LED epi-films 206, the surfaces of the supporting members can be held by a vacuum holding tool, or by a photocurable adhesive sheet of the type that loses its adhesion by exposure to light, for easy transportation.
The LED epi-films 206 are transported from the fabrication substrate 324 to a silicon wafer that constitutes the silicon substrate 201 of the compound semiconductor chips 200. The second interlayer dielectric film 209 is deposited on the wafer surface and patterned by photolithography to form a mask for the zinc diffusion process, which is now carried out to form the diffusion regions 216 shown in FIG. 6, thereby creating the LEDs. Performing the zinc diffusion process on the silicon wafer substrate ensures that the LEDs in each compound semiconductor chip 200 are evenly spaced. Next, a layer of metal is deposited and patterned to form the discrete electrodes 207 and other necessary interconnection wiring, after which wafer is diced into chips.
FIG. 9 is a schematic sectional view of a conventional LED head 119 employing combined semiconductor chips 200 of the conventional type described above. The printed circuit board 220 that was shown in FIG. 3 rests on a base 231. The LED head 119 also has a rod lens array 232 including a large number of cylindrical optical elements, a holder 233 for holding the rod lens array 232, and a clamp 234 for fastening the base 231, rod lens array 232, and holder 233 together. Light emitted by the combined semiconductor chips 200 passes through the rod lens array 232 and illuminates the photosensitive drum (not shown) in a printer. The width W0 of the LED head 119 must be adequate to accommodate the width of the combined semiconductor chips 200 and the bonding pads and wires (not shown) that connect them electrically to the printed circuit board 220.
For reasons that will now be explained, it has proven difficult to reduce the size and cost of the LED head as much as would be desirable.
In the conventional scheme illustrated in FIG. 2, with separate LED array chips and driver chips, the cost of wire bonding and the size of the LED array chips and driver chips are major factors that drive up the cost of the LED head. In particular, the material cost of the compound semiconductor LED array chips is high. One factor in the comparatively large size of the LED array chips and driver chips is the large number of space-consuming bonding pads needed to interconnect them. Another factor is the large size of the transistors in the drivers (DR1 . . . in FIG. 2) that drive the LEDs. The large size of the driving transistors is dictated by the need to supply the current consumed by the LEDs in generating light. Yet another factor is the need for memory elements (MEM1 . . . in FIG. 2) to store correction data.
If the LEDs are formed in epi-films disposed on the driving ICs, as FIGS. 3-9, compound semiconductor material costs and wire-bonding costs can be reduced, but the problem of the size of the driving circuits and the need to store correction data still remains. The conventional LED head disclosed in JP/2004-207444 permits the use of various compound semiconductor materials, such as GaAs, GaP, AlGaAs, InGaAsP, and InGaAlAs, for the light-emitting elements, but whichever of these materials are used, the light-emitting elements inevitably differ in their light-emitting characteristics because of crystal lattice defects etc. Compensation for variation in light-emitting efficiency is essential if printed output of high quality is to be obtained.
A further problem is that, because some of the compound semiconductor processing steps that form the LEDs, such as p-type impurity diffusion, are performed after the LED epi-films have been attached to the silicon wafer substrate, and because wiring must be formed in this state, diffusion and wiring defects can render both an LED array and its driving circuit useless. Consequently, the yield of combined semiconductor chips per wafer is lower than the yield when the LED array chips and driver ICs are fabricated separately.
Another problem is that, although the conventional configuration as disclosed in JP/2004-207444 lowers the compound semiconductor material cost, additional fabrication steps are required, so that the cost of the semiconductor fabrication process becomes an obstacle to reducing the cost of the LED head.